ASIC Static Timing Analysis Engineer by Google

February 22, 2024
ASIC Static Timing Analysis Engineer by Google

Job Description

About the job:

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  • 12 years of experience in silicon timing closure and chip integration.
  • Experience with STA sign-off constraint authoring for full-chip level, tape-out sign-off requirements, checklists, and associated automation.
  • Experience in one or more static timing tools: PrimeTime, Tempus, Timing Closure, STA, Timing ECO using Tweaker, Primeclosure, DMSA.

Preferred qualifications:

  • Master’s degree in Electrical Engineering.
  • Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
  • Knowledge of semiconductor device physics and transistor characteristics.


  • Drive the sign-off timing convergence for high performance designs.
  • Set up timing constraints, defining the overall Static Timing Analysis¬†(STA)¬†methodology.
  • Set up the STA infrastructure and sign-off convergence flows.
  • Work closely with block owners throughout the project for sign-off timing convergence.