RTL Design Engineer Posts by Google

February 21, 2024
RTL Design Engineer Posts by Google

Job Description

About the job:

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience
  • 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture
  • Experience with ARM-based SoCs, interconnects and ASIC methodology

Preferred qualifications:

  • Master’s degree in Electrical/Computer Engineering
  • 3 years of experience with IP design for clocking, interconnects, peripherals
  • Experience with methodologies for low power estimation, timing closure, synthesis
  • Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC)


  • Define the block level design document (i.e., interface protocol, block diagram, transaction flow, pipelines, etc.),
  • Perform RTL development (i.e. coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
  • Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
  • Participate in test plan and coverage analysis of the block and SoC-level verification.
  • Communicate and work with multi-disciplined and multi-site teams.