Senior Physical Design Engineer, Google Cloud Posts by Google

February 21, 2024
Senior Physical Design Engineer, Google Cloud Posts by Google

Job Description

About the job:

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you’ll solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering or equivalent practical experience.
  • 7 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
  • Experience with System on a Chip (SoC) cycles.
  • Experience in high-performance, high-frequency, and low-power designs.

Preferred qualifications:

  • Master’s degree in Electrical Engineering.
  • Experience in coding with System Verilog and scripting with TCL.
  • Experience with VLSI design in SoC or multiple-cycles of SoC in ASIC design.
  • Experience with layout verification and design rules.

Responsibilities:

  • Define and drive the implementation of physical design methodologies.
  • Take ownership of one or more physical design partitions or top level.
  • Manage timing and power consumption of the design.
  • Contribute to design methodology, libraries, and code review.
  • Define the physical design related rule sets for the functional design engineers.