Silicon Design Verification Engineer Posts by Google

February 21, 2024
Silicon Design Verification Engineer Posts by Google

Job Description

About the job:

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
  • 2 years of experience in Design Verification.

Preferred qualifications:

  • Master’s degree or PhD in Electrical Engineering or Computer Science.
  • Experience prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms.
  • Experience with performance verification of ASIC components.
  • Experience creating/using verification components and environments in methodology.
  • Experience with image processing, computer vision, or machine learning applications.
  • Experience with ASIC standard interfaces and memory system architecture.

Responsibilities:

  • Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog, or formally verify designs with industry leading formal tools.
  • Identify and write coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.