SoC Power Architect Posts by Google

February 21, 2024
SoC Power Architect Posts by Google

Job Description

About the job:

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering or equivalent practical experience
  • 5 years of experience in the semiconductor industry with a focus on low power
  • Experience in pre-si power analysis or post-si power characterization and analysis

Preferred qualifications:

  • Experience with competitive power and performance measurements and analysis for consumer electronics’ SoCs
  • Experience with ASIC design flows from concept to post-silicon
  • Experience with post-si power and performance characterization and analysis
  • Good understanding of SoC architectures, major IPs (CPU, GPU, memory), power trees, power delivery networks, and power management techniques used in consumer electronic devices
  • Familiarity with PMIC, SMPS, LDO, and power delivery networks

Responsibilities:

  • Define and drive low power solutions for Google SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints.
  • Drive PPA characterization and analysis for Google and competitor SoCs, including but not limited to power breakdowns, power benchmarking, IP-level power, use case power and performance, thermals, power efficiency, etc.
  • Perform post-silicon characterization and productization of power features.
  • Perform breakdowns of competitor devices’ to enable IP level power measurements and analysis.
  • Propose and drive power optimizations throughout the design process from concept to mass productization.