Google – Senior Design Verification Engineer, Google Cloud

August 13, 2023
Google – Senior Design Verification Engineer, Google Cloud

Job Description

Minimum qualifications:
Bachelor’s degree in Electrical Engineering or equivalent practical experience.
10 years of experience in Verification, verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.
Experience creating and using verification components and environments in standard verification methodology.

Preferred qualifications:
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
Experience with verification techniques and the full verification lifecycle.
Experience with performance verification of ASICs and ASIC components.
Experience with multiple SoC projects/cycles in 3 or more products.
Experience with ASIC standard interfaces and memory system architecture.
About the job
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As an Executive Design Verification Engineer, you will use design and verification expertise to verify complex digital designs. You will collaborate closely with design and verification engineers in active projects and perform verification. Using Universal Verification Methodology (UVM) and SystemVerilog coding and problem-solving skills, you will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology. Verify designs with SystemVerilog Assertions and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.