Google – Test Lead, SoC Design, Google Cloud

August 13, 2023
Google – Test Lead, SoC Design, Google Cloud

Job Description

Minimum qualifications:
15 years of experience in DFT specification definition architecture and insertion.
Experience using electronic design automation (EDA) test tools (e.g. Spyglass, Tessent, etc.).
Experience with ASIC DFT synthesis, simulation, and verification flow.
Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues).

Preferred qualifications:
Master’s degree in Electrical Engineering.
Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
Experience in fault modeling.
Experience in SoC cycles, including silicon bringup and silicon debug activities.
About the job
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As an SoC Design For Test Lead, you will work as part of a Research and Development team to lead and drive complex technical projects from the concept/planning stage through execution and closure. As part of our Server Chip Design team, you will use your design and verification testing expertise to verify complex digital designs. You will collaborate closely with Design, SoC, and Verification Engineers on active projects and perform Design for Test. You will be responsible for the full lifecycle of our DFT efforts, which can include test execution, DFT flow development, and overall production quality.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Own DFT logic and pre-silicon verification to collaborate with Test Engineers post-silicon, and develop DFT strategy and architecture, including hierarchical DFT, MBIST, and ATPG.
Complete all test design rule checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Drive DFT logic, including boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
Lead MBIST logic including test collar around memories, MBIST controllers, and eFuse logic, and connect to core and TAP interfaces.
Lead a team of Chip Engineers, plan tasks, allocate people, and manage the overall DFT flow development successfully. Document DFT architecture and test sequences, including boot-up sequence associated with test pins.