Google – Analog and Mixed Signal IP Validation Engineer, Silicon
Job Description
Minimum qualifications:
Bachelor’s degree in Electrical Engineering, Electronics Engineering or equivalent practical experience.
Experience working in a lab environment and automating bench equipments such as System Management Unit (SMU), Power supplies, Oscilloscope.
Experience with analog and mixed signal circuits such as PLL, ADC, DAC.
Preferred qualifications:
Experience in using benchtop equipment such as Digital Multimeter, Oscilloscopes, Power Analyzer, Phase Noise Analyzer.
Experience with schematic/layout reading, board level hardware debug.
Experience coding with Python/C++.
Experience working in a collaborative environment.
Knowledge of Linux OS, shell scripting, high speed Interfaces (e.g., USB, PCIE), Serializer/Deserializer (SERDES).
Knowledge of Circuit Analysis, Digital VLSI and Test methodologies.
About the job
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a key member of the team, you manage projects in multiple areas with your expertise. You also monitor the performance of vendors working on projects and evaluate new technologies.
As an Analog and Mixed Signal (AMS) IP validation engineer, you’ll help evaluate, test, characterize and qualify AMS IPs that are part of Google’s premium tier SoCs that power mobile phones, wearables, tablets and laptops.
In this role, you will be responsible for all aspects of post-silicon validation for AMS IPs (e.g., Phase Lock Loop (PLL), Frequency-Locked Loop (FLL), Analog-to-Digital Converter (ADC), current sensor, temp sensor, droop detector). You’ll work closely with ASIC Architecture, Design and DFT teams in pre-silicon stages to identify, advocate and implement Design for Test/Manufacturing/Debug strategies. You will be responsible for Bare Metal Bench level Signal/Power Integrity and protocol validation, review/audit IP compliance reports, Production Verification Testing (PVT) characterization, ATE-Bench correlation, SLT-Bench correlation and support cross-functional debugging.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Responsibilities
Design Google’s future products by owning bench level design validation and characterization for Analog and Mixed SIgnal (AMS) IPs (e.g., PLL, FLL, ADC, Current sensor, Temp sensor, Droop detector).
Work with Design and Domain Validation (DV) team to create bare metal bench test cases for IP validation as well as ASIC Architecture, Design, Pre-silicon SoC to implement end-to-end manufacturing test solutions.
Work with all cross-functional teams (e.g., Design, System Architecture, DV, software, program management, operations) to deliver products in the market.
Work with the productization test teams to develop effective production screens.
Characterize IP specific Signal Integrity, Power Integrity and performance test cases to evaluate IP performance at various operating conditions (e.g., voltage, process, temperature).
