Google – Physical Design Engineer, Silicon, Google Cloud
Job Description
Minimum qualifications:
Bachelor’s degree in Electrical Engineering or equivalent practical experience.
4 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
Experience with System on a Chip (SoC) cycles.
Experience with performance, frequency, and low-power designs.
Preferred qualifications:
Master’s degree in Electrical Engineering, or a related field.
Experience coding with System Verilog and scripting with TCL.
Experience with multiple-cycles of SoC in ASIC design.
Experience with layout verification and design rules.
Experience with VLSI design in SoC.
About the job
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. You will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
Responsibilities
Define and drive to the implementation of physical design methodologies.
Take ownership of one or more physical design partitions or top-level.
Drive to the closure of timing and power consumption of the design.
Contribute to design methodology, libraries, and code review.
Define the physical design related rule sets for the functional design engineers.
